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<title><![CDATA[Comentarios al libro: DESIGN-FOR-TEST AND TEST OPTIMIZATION TECHNIQUES FOR TSV-BASED 3D STACKED ICS]]></title>
<link><![CDATA[https://api.biblioeteca.com/biblioeteca.web/titulo/design-for-test-and-test-optimization-techniques-for-tsv-based-3d-stacked-ics]]></link>
<description><![CDATA[This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.]]></description>
<lastBuildDate>Sat, 06 Jun 2026 09:40:38 +0000</lastBuildDate>
<language>es</language>
<copyright>Copyright 2021 BiblioEteca Technologies SL</copyright>

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