<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0">
<channel>
<title><![CDATA[Comentarios al libro: LOW POWER DESIGN WITH HIGH-LEVEL POWER ESTIMATION AND POWER-AWARE SYNTHESIS]]></title>
<link><![CDATA[https://api.biblioeteca.com/biblioeteca.web/titulo/low-power-design-with-high-level-power-estimation-and-power-aware-synthesis]]></link>
<description><![CDATA[This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.]]></description>
<lastBuildDate>Tue, 02 Jun 2026 23:15:42 +0000</lastBuildDate>
<language>es</language>
<copyright>Copyright 2021 BiblioEteca Technologies SL</copyright>

</channel>
</rss>
