SYSTEMVERILOG FOR VERIFICATION

In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students? understanding of the material. Other features of this revision include:

• New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard
• Descriptions of UVM features such as factories, the test registry, and the configuration database
• Expanded code samples and explanations
• Numerous samples that have been tested on the major SystemVerilog simulators

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.

Idioma: INGLÉS